`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:56:22 05/19/2014 
// Design Name: 
// Module Name:    test_MontProd 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`define BITS 16

module test_MontProd(
    );

reg clk = 0;
reg start;
reg [`BITS-1:0] A, B, M;
wire [`BITS-1:0] result;
wire done;


MontProd m1(
	clk,
	start,
	A,
	B,
	M,
	done,
	result
);

	always #10 clk = ~clk;
	
	initial 
	begin
	  #0 		start = 0;	
	  #40		A		= `BITS'hBE;
	  #40 	B		= `BITS'hBE;
	  #40 	M		= `BITS'd1189; 
	  #40    start	= 1; 
	  #10000 
	  $stop;  
	end

endmodule
